About Covered
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable...
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
Previous Versions
Here you can find the changelog of Covered since it was posted on our website on 2015-04-25 03:00:00.
The latest version is 0.7.10 and it was updated on 2024-04-19 23:41:34. See below the changes in each version.
Covered version covered-0.7.10
Updated At: 2010-12-02
Changes: Several fixes and updates
Covered version covered-0.7.10
Updated At: 2010-12-02
Disclaimer
External Download
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